The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to methods of fabricating memory and related devices.
As a semiconductor device becomes highly integrated, stable operations of a transistor may not be ensured. Research into a buried channel array transistor (BCAT) has been extensively conducted to overcome a short channel effect and to reduce the size of a transistor.
The BCAT may be formed to bury a gate electrode in a semiconductor substrate. A capping pattern may be provided on the buried gate electrode. An upper surface of the capping pattern may be formed at the same level as that of the semiconductor substrate. That is, the buried gate electrode may be covered with the capping pattern, and provided at a lower level than the upper surface of the semiconductor substrate. Source and drain regions may be provided at both sides of the buried gate electrode in the semiconductor substrate. As a result, the BCAT may have a longer effective channel length than a planar transistor. In other words, the BCAT may have a structure suitable for high integration density.
Semiconductor devices such as a dynamic random access memory (DRAM) may include a plurality of BCATs. Also, the semiconductor devices may adopt interconnections such as bit lines and buried contact plugs as components. For example, the semiconductor substrate having the BCAT may be covered with an interlayer insulating layer. The bit line may be disposed in the interlayer insulating layer. The bit line may be in contact with selected one of the source and drain regions by a bit plug passing through the interlayer insulating layer. A storage node may be disposed on the interlayer insulating layer. The storage node may be in contact with the other of the source and drain regions by a buried contact plug passing through the interlayer insulating layer.
The buried contact plug should be insulated from the bit line and the bit plug. Meanwhile, as the BCAT is fabricated to be reduced, a space on which the buried contact plug can be disposed may become narrower. That is, forming the buried contact plug to be insulated from the bit line and the bit plug may become difficult.
Another method of forming a contact plug on a semiconductor substrate is disclosed in U.S. Patent Publication No. U.S. 2006/0276019 entitled “Method for Production of Contacts on a Wafer” to Graf.
According to Graft a method of forming contact holes using a bar-type mask pattern formed by a photolithography process may be provided. In this case, the size of the contact holes and the distance between the contact holes are determined by resolution limit of photolithography. In other words, there may be a limit in reductions to the size of the contact holes and the distance between the contact holes.